1. Field of the Invention
The invention relates generally to a multiprocessor system and, more particularly, to maintaining identical bus delays for different processors in a multiprocessor system.
2. Description of the Related Art
In a switch-based multiprocessor system using high-speed, source-clocked, unidirectional point-to-point busses, with different wiring delay timing differences between busses, the natural choice for implementation of a snoop based protocol, would be to allow variations in snoop address and snoop response times. However, this introduces complexity in the design.
In a standard snoop protocol used in a signal bus, bus masters, which take control of the bus, arbitrate for the bus and present their address and command on the bus when access is granted. Each processor or memory controller attached to the bus sees the address and command at the same time and generates its snoop response at a time specified by the bus architecture. Then, the snoop response becomes valid after the snoop request has been received by the snooping memory controller and processor.
In a multiprocessor system, two or more processors source commands and addresses on processor outbound busses to a memory controller. Typically, the memory controller may function as a bus switch and an address switch. The memory controller arbitrates between the processor busses, selecting one processor outbound command to reflect back to all the processors, via processor inbound busses. Since there may be wiring delay differences between the processor inbound busses, a command provided to the processors at the same memory controller clock may not arrive at the processors at the same time. Similarly, when the multiprocessor system has point-to-point, unidirectional, source-clocked snoop response busses, these busses carrying snoop responses may also have wiring delay differences between the processors.
The differences in bus delays complicate the snoop protocol, if differences are allowed between when each processor observes the snoop response for a particular snoop. In addition, the memory controller job of combining the snoop responses is more difficult, if the memory controller sees the responses for a particular snoop at different times from each processor.
Therefore, there is a need for aligning the snoop addresses and snoop responses across all busses. This would allow the snoop protocol to be a simple variant of single bus based snoop protocol.